In fabricating field effect transistors (“FETs”) in semiconductor wafers, source and drain regions are implanted which have p-type or n-type conductivity. However, for complementary metal oxide semiconductor (CMOS) devices, source and drain regions are implanted with a p-type dopant to form p-type FETs (“PFETs”), and source and drain regions are implanted with an n-type dopant to form n-type FETs (“NFETs”). It has been demonstrated that carrier mobility in a transistor can be increased when a stress of sufficient magnitude is applied to the conduction channel of a transistor to create a beneficial strain therein. An increase in the performance of an n-type field effect transistor (NFET) can be achieved by applying a tensile stress to the conduction channel of the NFET in a longitudinal direction of the conduction channel. An increase in the performance of a p-type field effect transistor (PFET) can be achieved by applying a compressive stress to the conduction channel of the PFET in a longitudinal direction of the conduction channel.
A stress-imparting film, also referred to herein as a “stressed” film, can be deposited to cover a semiconductor device region to impart a stress thereto for enhancing the conductivity of a transistor, for example, an NFET or a PFET device. Silicon nitride is one material, among others, which can be deposited in such way that the resulting material layer imparts either a tensile stress or a compressive stress to a layer of a second material with which it is in contact. To enhance the conductivity of circuits which include both an NFET and a PFET, a tensile stressed silicon nitride layer can be formed to cover an active semiconductor region of the NFET and a compressive stressed silicon nitride layer can be formed to cover an active semiconductor region of the PFET.
From a fabrication point of view, such a goal can be accomplished by forming two films, each having a different internal stress, to overlie the NFET and PFET. In such case, a tensile stressed film 102 can be deposited and patterned to overlie an active semiconductor region 132 in which the NFET is provided, after which a compressive stressed film 104 is deposited and then patterned to overlie another active semiconductor region 134 in which the PFET is provided. Typically, the two stressed films are overlapped at an overlap region 100, as illustrated in FIG. 1. However, overlapped films can create certain problems.
One problem involves forming a conductive via 210 for contacting gate conductors of the NFET and PFET. As seen in FIG. 1, a gate conductor 122 of the NFET and a gate conductor 124 of the PFET are joined together in an overlapped region overlying a trench isolation region 110 of a chip. In one example, the gate conductors can include a polysilicon conductor 225 with an overlying low-resistance layer, such as a layer 227 including a metal or conductive metal compound such as a silicide. The etching of the contact hole in the overlapped region 100 between the two active semiconductor regions can be difficult to perform while etching other contact holes, such as a contact hole 212 in which a contact via to a source region or drain region of the PFET will be formed. The difficulty arises because of the relative differences in thickness between the film 104 where the contact via 212 is formed and the combined thicknesses of the stressed films 102 and 104 through which the contact hole 210 is formed. As apparent from FIG. 1, the combined thicknesses of the stressed films 102, 104 where overlapped at the boundary 220 are much greater than the thickness of the film 104 where the contact via 212 is formed. The difference in the combined thickness of the two films 102, 104 versus the thickness of the one film 102 relative thereto can make it difficult to simultaneously form a contact via to at least one of the gate conductors through contact via 210 and to form a contact via 212 to a source region or a drain region of a transistor, e.g. the PFET.
As seen in FIG. 2, a contact open failure (as shown generally at location 220) can result where the contact via 210 extends through both stressed films 102, 104 at the overlapped region 100 at location 220 where the two stressed films meet over the trench isolation region 110. A contact open failure occurs when there is much higher than normal resistance at the interface between the conductive contact via 210 and the low-resistance layer 227 or polysilicon layer 225 of the gate conductor. A contact open failure can occur when an etching process fails to etch the contact hole fails to a sufficient depth. The problem is more difficult to solve than simply extending the time of etching or increasing the strength of the etchant to increase the depth of the contact hole. When the depth to which the contact hole 210 is etched is extended, “over”-etching of the contact hole 212 (FIG. 1) can occur. As a result, the contact hole 212 may extend too deeply, such that it etches through most or all of the low-resistance layer 277 and into the semiconductor region in which the source region or drain region is provided.
FIG. 3 is a plan view illustrating an alternative arrangement in which a gate conductor 322 of a NFET and a gate conductor 324 of a PFET extend parallel to each other. In this case, the stressed films 302, 304 are overlapped in an overlapped region 300 spaced from each of the two gate conductors. Embodiments of the invention herein are also described in relation to the arrangement illustrated in FIG. 3.
From the foregoing it is apparent that a need exists for a structure and an associated method of fabricating a semiconductor device in which more than one stressed films can be provided, while permitting contact vias to be etched with less difficulty.